LEON
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LEON is a 32-bit CPU microprocessor core, based on the SPARC-V8 RISC architecture and instruction set. It was originally designed by the European Space Research and Technology Centre, part of the European Space Agency, and after that by Gaisler Research. It is described in synthesizable VHDL, with a GNU General Public License for LEON3 versions and GNU Lesser Public License for LEON1 and LEON2 versions [1][2].
The core is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs.
LEON2
The centre of reusable component is the Leon2 processor, a SPARC V8 compliant processor whose VHDL description is freely available on the Internet under the GNU LGPL. Leon2 has many interesting characteristics.
- It is well-known in the community, widely tested and centrally maintained, thereby offering good applicability range.
- The LGPL allows a high degree of freedom of intervention on the freely-available source code.
- Configurability is a key feature of the project.
- It offers all basic functions of a pipelined in-order processor, making it a good experimentation vehicle.
- It is a fairly-sized VHDL project (about 90 files), offering all the challenges of large-scale interventions on great projects.
LEON2-FT
The LEON2-FT processor is the single event upset tolerant version of the LEON2 processor. Flip-flops are protected by triple modular redundancy and all internal and external memories are protected by EDAC or parity bits. Special licence restrictions apply to this IP (distributed by the European Space Agency [3]).
LEON3
The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores.
LEON3-FT
The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single event upset (SEU) errors in all on-chip RAM memories. The LEON3FT processor support most of the functionality in the standard LEON3 processor, and adds the following features:
- Register file SEU error-correction of up to 4 errors per 32-bit word
- Cache memory error-correction of up to 4 errors per tag or 32-bit word
- Autonomous and software transparent error handling
- No timing impact due to error detection or correction
The following features of the standard LEON3 processor are not supported by LEON3FT
- Local scratchpad RAM (I and D)
- Cache locking
- LRR cache replacement algorithm
The LEON3FT core is distributed together with a special FT version of the GRLIP IP library. Only netlist distribution is possible.
A FPGA implementation called LEON3FT-RTAX is proposed for critical space applications.[4]
LEON can be implemented in programmable logic such as an FPGA or manufactured into an ASIC. Implementing and simulating LEON is hardware–software codesign and requires knowledge about system-on-a-chip design flow.
Documentation of the LEON design flow is available both from the manufacturer[5] and from third party resources.[6][7]
See also
References
- ^ "European Space Agency launches free Sparc-like core", Peter Clarke, EE Times, 03/06/2000 [1]
- ^ Free Sparc processor developer goes Commercial, Peter Clarke Silicon Strategies, EEtimes , 02/24/2005 [2]
- ^ European Sapce Agency IP Cores Library LEON-2 FT page
- ^ Gaisler Research, LEON3FT-RTAX Fault-tolerant Processor
- ^ Gaisler Research, GRLIB User's Manual
- ^ Buttelmann, A nice LEON3 simulation guide
- ^ Buttelmann, Xilinx LEON 3 blockdiagram