MMX (instruction set)

Pentium with MMX

MMX is a single instruction, multiple data (SIMD) instruction set designed by Intel, introduced in 1996 with their Pentium line of microprocessors, designated as "Pentium with MMX Technology". It developed out of a similar unit first introduced on the Intel i860. MMX is a processor supplementary capability that is supported on recent IA-32 processors by Intel and other vendors.

Intel's competitor AMD enhanced Intel's MMX with the 3DNow! instruction set to work with floating-point numbers. Intel would follow AMD's lead on floating-point math and created the SSE extension a year after 3DNow! was introduced.

Naming

MMX is officially a meaningless initialism trademarked by Intel; unofficially, the initials have been variously explained as standing for MultiMedia eXtension, Multiple Math eXtension, or Matrix Math eXtension.

AMD, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions". The idea that it stands for nothing is an Intel corporate position meant to suggest that it is of trademarked status and cannot be used by AMD or other x86 clone manufacturers in their own marketing material.

Technical details

Pentium II processor with MMX technology

MMX defined eight registers, known as MM0 through MM7 (henceforth referred to as MMn). To avoid compatibility problems with the context switch mechanisms in existing operating systems, these registers were aliases for the existing x87 FPU stack registers (so no new registers needed to be saved or restored). Hence, anything that was done to the floating point stack would also affect the MMX registers and vice versa. However, unlike the FP stack, the MMn registers are directly addressable (random access).

Each of the MMn registers holds 64-bits (the mantissa-part of a full 80 bit FPU register). The main usage of the MMX instruction set is the concept of packed data types, which means that instead of using the whole register for a single 64-bit integer, two 32-bit integers, four 16-bit integers, or eight 8-bit integers may be processed concurrently.

The mapping of the MMX registers onto the existing FPU registers made it somewhat difficult to work with floating point and SIMD data in the same application. To maximize performance, programmers often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.

Because the FPU stack registers is 80 bits wide, the upper 16 bits of the stack registers go unused in MMX, and these bits are set to all ones, which makes them NaNs or infinities in the floating point representation. This can be used to decide whether a particular register contents was intended as floating point or SIMD data.

MMX provides only integer operations. When originally developed, for the Intel_i860, the use of integer math made sense (both 2D and 3D calculations required it), but as graphics cards that did much of this became common, integer SIMD in the CPU became somewhat redundant for graphical applications. On the other hand, the saturation arithmetic operations in MMX could significantly speed up some digital signal processing applications.

Successor

Intel addressed the shortcomings of the MMX technology through SSE, a greatly expanded set of SIMD instructions with 32-bit floating point support and an additional set of 128-bit vector registers that made it easy to perform SIMD and FPU operations at the same time. SSE was in turn expanded with SSE2, which also extended MMX instructions so they can operate on 128-bit XMM registers (later SSE extensions would still support operating integer data on MMX registers because the new SSE registers require OS support, until SSE4, which ended this support) and recently with SSE4.2, introduced in the Intel Core microarchitecture. Support for any of these later instruction sets implies support for MMX.

MMX in embedded applications

Intel's XScale processors starting with PXA270 include an extension to the ARM core called iwMMXt whose functions are similar to those of the IA-32 MMX extension. IwMMXt stands for "Intel Wireless MMX Technology". It provides arithmetic and logic operations on 64-bit integer numbers (the software may choose to instead perform two 32-bit, four 16-bit or eight 8-bit operations in a single instruction). The extension contains 16 data registers of 64-bits and eight control registers of 32-bits. All registers are accessed through standard ARM architecture coprocessor mapping mechanism. iwMMXt occupies coprocessors 0 and 1 space, and some of its opcodes clash with the opcodes of the earlier floating-point extension, FPA.

External links

• Intel Pentium Processor with MMX Technology Documentation
• The MMX Instruction Set from The Art of Assembly Language
• IA Software Developer's Manual, Vol 1 (PDF), see chapter 8 for MMX programming