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Thus, in its selection of registers, the ND-500 processor more strongly resembles the ND-100 which, at each priority level, provides a single accumulator (A), index register (X), base register (B), extension register (D), program counter (P), link register (L), along with a temporary register (T) mostly used for floating-point operations, and a status register (STS). Unlike the ND-500, the ND-100 preserves the fixed-size, 16-bit instruction format of the earlier Nord-10 series, but like the ND-500, the ND-100 processor is microprogrammed.<ref name="ND-06.014.02">{{ cite book | url=http://heim.bitraf.no/tingo/files/nd/ND-06.014.02_ND-100_Reference_Manual_January_1982_ocr.pdf | title=ND-100 Reference Manual | publisher=Norsk Data AS | date=January 1982 | access-date=4 September 2024 | issue=2 }}</ref>{{rp|pages=2-1,2-6,3-1}}
Thus, in its selection of registers, the ND-500 processor more strongly resembles the ND-100 which, at each priority level, provides a single accumulator (A), index register (X), base register (B), extension register (D), program counter (P), link register (L), along with a temporary register (T) mostly used for floating-point operations, and a status register (STS). Unlike the ND-500, the ND-100 preserves the fixed-size, 16-bit instruction format of the earlier Nord-10 series, but like the ND-500, the ND-100 processor is microprogrammed.<ref name="ND-06.014.02">{{ cite book | url=http://heim.bitraf.no/tingo/files/nd/ND-06.014.02_ND-100_Reference_Manual_January_1982_ocr.pdf | title=ND-100 Reference Manual | publisher=Norsk Data AS | date=January 1982 | access-date=4 September 2024 | issue=2 }}</ref>{{rp|pages=2-1,2-6,3-1}}

Promotional materials for the ND-500 emphasised the "highly symmetric" or [[Orthogonal instruction set|orthogonal]] instruction set, permitting the use of all addressing modes with all instruction types and with all data types, providing memory-to-memory instructions able to retrieve operands, perform computational operations, and store results. Such materials claimed a higher code density than most 16-bit computers despite the 32-bit nature of the ND-500 processor.<ref name="ND-060-C1-EN">{{ cite book | url=http://norsk-data.com/library/libpdpi/ND-060-C1-EN.pdf | title=ND-500 Central Processing Unit | publisher=Norsk Data AS | date=April 1981 | access-date=7 September 2024 }}</ref>{{rp|pages=5}}


== Hardware implementations ==
== Hardware implementations ==

Revision as of 15:28, 7 September 2024

A typical large ND-500 configuration.

The ND-500 was a 32-bit superminicomputer delivered in 1981 by Norsk Data priced from £75,000 for the base model. It relied on a ND-100 to do housekeeping tasks and run the OS, SINTRAN III.[1] A configuration could feature up to four ND-500 CPUs in a shared-memory configuration.

System architecture

The ND-500 combined a 32-bit system based on one or more Nord-500 or ND-500 processors with a ND-100 minicomputer responsible for input/output handling, job scheduling, management of the ND-500 system, and providing a multi-user environment based on the SINTRAN III/VS operating system. This arrangement largely preserved the general architecture of systems based on the preceding Nord-5 and Nord-50 models, and in keeping with those models, the 32-bit component of the ND-500 was aimed at "simulation, numerical analysis and scientific" workloads.[2]

The ND-500 processor employed split data and instruction caches, running with a 110 nanosecond cycle time, along with similarly separated memory management units, thus permitting access to a full 32-bit address space for both program instructions and data. A total 32 MB of physical memory was supported. Physical memory was shared between the ND-100 and ND-500 systems, exposed in a "multiport" arrangement, with the ND-500 having two paths to this RAM, the ND-100 having one path, and the direct memory access hardware having its own path. A prefetch processor was used to decode instructions fetched from memory, to populate the execution pipeline, and to initiate memory accesses for referenced addresses. This processor operated concurrently with the arithmetic logic unit.[2]

Processor architecture

The instruction set of the ND-500, featuring "184 basic instruction codes" specialised by several data types and addressing modes, along with "few and specialized" registers, lent itself to an instruction encoding of only one or two bytes, albeit with the potential for several accompanying operands, up to 256 in number.[3] Operands could be from one to nine bytes in length, and thus the documentation for the ND-500 notes, "The shortest instructions are one byte long, the longest may be several thousand bytes long."[4]: 117  This contrasted strongly with the design of the CPU in its predecessor, the Nord-50, which featured 32-bit instructions in only three formats and the availability of 64 general-purpose registers.[5]

The ND-500 processor provides only four 32-bit registers for use as integer accumulators or index registers, I1 through I4, and four 32-bit registers for use as floating-point accumulators, A1 through A4, each extended by one of four extension registers, E1 through E4, to provide 64-bit registers for double-precision floating-point operations. Base registers B and R provide access to local variables and record storage respectively. Several other special-purpose registers are provided such as the program counter (P), link or subroutine return address (L), top-of-stack (TOS), plus registers related to trap handling, processor status, and process characteristics. Of the 50 documented registers in the ND-500, several are reserved for use by the processor's microprogram.[4]

Thus, in its selection of registers, the ND-500 processor more strongly resembles the ND-100 which, at each priority level, provides a single accumulator (A), index register (X), base register (B), extension register (D), program counter (P), link register (L), along with a temporary register (T) mostly used for floating-point operations, and a status register (STS). Unlike the ND-500, the ND-100 preserves the fixed-size, 16-bit instruction format of the earlier Nord-10 series, but like the ND-500, the ND-100 processor is microprogrammed.[6]: 2–1, 2–6, 3–1 

Promotional materials for the ND-500 emphasised the "highly symmetric" or orthogonal instruction set, permitting the use of all addressing modes with all instruction types and with all data types, providing memory-to-memory instructions able to retrieve operands, perform computational operations, and store results. Such materials claimed a higher code density than most 16-bit computers despite the 32-bit nature of the ND-500 processor.[7]: 5 

Hardware implementations

In its first incarnation, the ND-500 was built using TTL integrated circuits, just as the Nord-50 had been.[3] The floating-point processor featured in the ND-500 reportedly consisted of 579 integrated circuits and used a combinatorial approach to support the execution of 64-bit multiplication operations in 480 nanoseconds.[8] Norsk Data claimed a Whetstone benchmark rating of 1.4 to 1.8 million single-precision Whetstone instructions per second for the ND-500.[3]

The ND-500 architecture lived through four distinct implementations. Each implementation was sold under a variety of different model numbers.

ND also sold multiprocessor configurations, naming them ND-580/n and an ND-590n, where n represented the number of CPUs in a given configuration, 2, 3, or 4.

ND-500/1

Sold as the ND-500, ND-520, ND-540, and ND-560.

ND-500/2

Sold as the ND-570, ND-570/CX, and ND-570/ACX.

The ND-500/CX series upgraded the ND-500 range during 1984, introducing the ND-530/CX, ND-550/CX, ND-560/CX and ND-570/CX in a range of different product variants, including the compact model III for the lower-end products. Advertised performance figures were given as 0.6, 1.3, 2.1 and 3.3 million Whetstone instructions per second for the respective products.[9]

ND-505

A 28-bit version of the ND-500 machine. Pins were snipped on the backplane, removing its status as a superminicomputer, allowing it to legally pass through the CoCom embargo.

Samson

Sold as the ND-5200, ND-5400, ND-5500, ND-5700, and ND-5800. The ND-120 CPU line, which constituted the ND-100 side of most ND-5000 computers, was named Delilah. As the 5000 line progressed in speed, the dual-arch ND-100/500 configuration increasingly became bottlenecked by all input/output (I/O) having to go through the ND-100.[citation needed]

The ND-5700, ND-5800 and ND-5900 were introduced in 1987 as high-end models, employing "state-of-the-art CMOS gate array technology" to reduce the footprint of the CPU implementation, replacing the 24 circuit boards required in the previous ND-500 architecture models. The ND-5900 was a multi-CPU model featuring two, three or four CPUs. Performance varied between the models, with the ND-5700 delivering half the performance of the ND-5800, and with the ND-5900 models respectively delivering two, three and four times the performance of the ND-5800.[10] Pricing for the models started at $400,000 for the ND-5700, reaching $1.53 million for the four-CPU ND-5900.[11]

Later models were introduced at the low end of the range in the form of the ND-5000 Compact series, aimed at small and medium-size companies and featuring a cabinet size with "modest dimensions", "occupying less than a square metre of floor space", and designed for a conventional office environment, as opposed to a dedicated machine room. Offered as the ND-5200 Compact, ND-5400 Compact, ND-5500 Compact and ND-5700 Compact, supporting smaller amounts of memory than the earlier ND-5000 models, performance of the high-end ND-5700 Compact was around that of the conventional ND-5700 model.[12]

The Compact series generally offered a reported 0.5 to 3.5 million Whetstone instructions per second across the different models. Norsk Data claimed that this was "the world's largest compatible range" of computers, or perhaps the industry's range with broadest performance characteristics across compatible models, with the top-end ND-5900 Model 4 delivering a claimed 26 million Whetstone instructions per second.[12][13][note 1]

Rallar

Sold as the ND-5830 and ND-5850. The Rallar processor consisted of two main VLSI gate arrays, KUSK (En: Jockey) and GAMP (En: Horse).[citation needed]

In 1988, with the introduction of Norsk Data's Extended System Architecture, this being the company's open systems strategy, two models of the ND-5000 ES (Extended Server) product were unveiled: the low-end Model S as an "affordable supermini in micro format", and the more powerful Model C as a departmental server based on the ND-5800 SE processor, yielding an almost two-fold performance improvement over earlier products.[14]

Alongside these newer ND-5000-based models, the company also introduced the ND-5100/xi system. Despite adherence to the existing naming convention, this was actually a system based on the Intel 80386 running SCO Xenix System V, offered in 14 different configurations.[14]

Software

LED was a programmer's source-code editor by Norsk Data running on the ND-500 computers running Sintran III. It featured automatic indenting, pretty-printing of source code, and integration with the compiler environment. It was sold as an advanced alternative to PED. Several copies exist, and it is installed on the NODAF public access ND-5700.

In 1984, Norsk Data contracted Logica to undertake a project to port Unix Berkeley Software Distribution (BSD) 4.2 to the ND-500/CX, this being described as Logica's first attempt to port BSD 4.2 despite "extensive experience with Microsoft's Xenix".[15] A C compiler from Luleå University College in Northern Sweden was used. The goal was to port Unix BSD to the ND-500 and use the ND-100 running Sintran-III as the front end. Thus, all I/O had to go through the ND-100 which proved very inefficient. For example, running vi on the ND-500 brought the ND-100 to its knees. The purpose of the effort was so that ND could sell the 500 to the European Organization for Nuclear Research (CERN), who were buying VAXes from Digital Equipment Corporation. But the ND-500 was unable to meet CERN's goals. Although the ND-500 processor was very fast for its time, it couldn't compete with the superior VAX I/O architecture.

With the launch of the ND-5000 Compact models in 1987, Norsk Data promised the later availability of a POSIX-compliant Unix system running concurrently with Sintran on the main ND-5000 processor, as opposed to running within Sintran, persisting with the use of Sintran on the front-end ND-100 series processor. These models also incorporated the Motorola 68020 as input/output controllers.[16]

References

  1. ^ Cahill, Kevin (9 April 1981). "Norsk launches first European 32-bit mini". Computer Weekly. p. 3. Retrieved 24 June 2024.
  2. ^ a b "16- and 32-Bit Computers Adapt Readily to Changing Requirements". Computer Design. September 1979. pp. 64–65. Retrieved 30 June 2024.
  3. ^ a b c Knudsen, Per (11 August 1982). "Supermini goes multiprocessor route to put it up front in performance" (PDF). Electronics. pp. 112–117. Retrieved 1 July 2024.
  4. ^ a b ND-500 Reference Manual (PDF). Norsk Data AS. June 1987. Retrieved 28 August 2024.
  5. ^ NORD-50 Reference Manual (PDF). Norsk Data AS. February 1976. Retrieved 26 August 2024.
  6. ^ ND-100 Reference Manual (PDF). Norsk Data AS. January 1982. Retrieved 4 September 2024.
  7. ^ ND-500 Central Processing Unit (PDF). Norsk Data AS. April 1981. Retrieved 7 September 2024.
  8. ^ Waser, Shlomo; Flynn, Michael J. (1982). Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing. p. 211. ISBN 0-03-060571-7. Retrieved 30 June 2024.
  9. ^ "The ND-500/CX Series – a new profile for high-end systems" (PDF). ND News. November 1984. p. 30. Retrieved 6 July 2024.
  10. ^ Bakke, Henrik; Moini, Zaira (March 1987). "The ND-5000 Series: Removing Hardware Limitations" (PDF). ND News. pp. 52–53. Retrieved 6 July 2024.
  11. ^ Connolly, James (23 February 1987). "Norsk adds high-end system to ND-5000 series". Computerworld. p. 48. Retrieved 9 July 2024.
  12. ^ a b Hasting, Arvid (September 1987). "Powerful Computers Now also for Smaller Companies" (PDF). ND News. pp. 70–71. Retrieved 6 July 2024.
  13. ^ Annual Report 1986 (PDF). Norsk Data. May 1987. p. 34. Retrieved 7 July 2024.
  14. ^ a b Jensen, Jan Roald (October 1988). "Product announcements" (PDF). ND News. pp. 40–42. Retrieved 6 July 2024.
  15. ^ "News in brief" (PDF). ND News. November 1984. p. 33. Retrieved 6 July 2024.
  16. ^ "Norsk Data Promises Posix, Fleshes out ND5000 Mini Line". Unigram/X. 22 August 1987. p. 3.

Notes

  1. ^ Note that Norsk Data uses the term "Mips" in its description of the Compact series, not explicitly referencing any industry-defined performance metric, leaving such figures open to interpretation. However, the 1986 annual report, published in 1987, indicates "26 Whetstone MIPS" for the cumulative performance rating of the four-CPU model.

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